Memory is one type of integrated circuitry, and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a sense line and an access line.
Memory cells may be volatile, semi-volatile, or nonvolatile. Nonvolatile memory cells can store data for extended periods of time in the absence of power. Nonvolatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates, and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.
One type of memory cell has at least one transistor and at least one capacitor. In some such structures, one conductive via extends downwardly from a sense line to one source/drain region (e.g., a circuit node) of the transistor. Additionally, another conductive via may be laterally-adjacent the one conductive via and extend downwardly from a storage node of the capacitor to another source/drain region of the same or another transistor. Unfortunately, parasitic capacitance exists laterally between the one conductive via and the other conductive via. Such parasitic capacitance can adversely affect circuit performance. Parasitic capacitance laterally between conductive vias in other circuitry can also adversely affect circuit performance. Parasitic capacitance may be reduced, for example, by using a combination of silicon nitride and silicon dioxide as insulative materials laterally between adjacent conductive vias. However, in circumstances where other regions of silicon dioxide are etched, that silicon dioxide that is laterally between adjacent conductive vias may also be undesirably etched if it is exposed to the etching conditions. This can possibly lead to electrical shorting of the laterally-adjacent conductive vias when conductive material is subsequently deposited.
While the invention was motivated in addressing and overcoming the above identified issues, it is not necessarily so limited.